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Author Nohbyung Park ♦ Parker, A.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1985
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Clocks ♦ Engines ♦ Digital systems ♦ Pipelines ♦ Contracts ♦ Buffer storage ♦ Partitioning algorithms ♦ Algorithm design and analysis ♦ Design optimization ♦ Phase estimation
Abstract Clocking scheme synthesis includes the partitioning of functions into time steps, the number of clock phases, the length of each phase, (i.e. how to pipeline) and the assignment of functions to clock phases; each of these choices affects performance. Some important problems of clocking scheme synthesis are examined. Two efficient and powerful algorithms which synthesize near optimal clocking schemes have been programmed. These algorithms are applied to synthesis and/or performance evaluation of a design in progress. Optimizing the speed of a previously designed system is also considered.
Description Author affiliation: Department of Electrical Engneering - Systems, University of Southern California, Los Angeles, CA (Nohbyung Park)
ISBN 0818606355
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1985-06-23
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 722.83 kB
Page Count 7
Starting Page 489
Ending Page 495


Source: IEEE Xplore Digital Library