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Author Tao Luo ♦ Newmark, D. ♦ Pan, D.Z.
Sponsorship SiCda ♦ EDA Consortium ♦ IEEE Circuits & Syst. Soc. ♦ IEEE CASS/CANDE ♦ CANDE ♦ CEDA
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2006
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Timing ♦ Wire ♦ Application specific integrated circuits ♦ Circuit testing ♦ Routing ♦ Algorithm design and analysis ♦ Linear programming ♦ Design methodology ♦ Delay effects ♦ Propagation delay ♦ Design ♦ Algorithms
Abstract In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advantage of the path-based delay sensitivity with limited-stage slew propagation, thus it enjoys certain hybrid feature of net and path-based timing driven placement. Our LP formulation considers not only cells on the critical paths, but also cells that are logically adjacent to the critical paths (i.e., the criticality adjacency network) in a unified manner. We further present a timing aware spreading method to preserve timing in legalization for high performance designs. Our algorithm has been tested on a set of 65nm industry circuits from a multi-GHz microprocessor, and shown to achieve much improved timing on hand-tuned circuits
Description Author affiliation: Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX (Tao Luo; Newmark, D.; Pan, D.Z.)
ISBN 1595933816
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2006-07-24
Publisher Place USA
Rights Holder Association for Computing Machinery, Inc. (ACM)
Size (in Bytes) 3.32 MB
Page Count 6
Starting Page 1115
Ending Page 1120


Source: IEEE Xplore Digital Library