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Author Gorjiara, B. ♦ Reshadi, M. ♦ Gajski, D.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2006
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Discrete cosine transforms ♦ Clocks ♦ Computer architecture ♦ Hardware ♦ Application specific processors ♦ Embedded computing ♦ Software performance ♦ Decoding ♦ Automatic generation control ♦ Frequency
Abstract This paper presents design of a custom architecture for discrete cosine transform (DCT) using no-instruction-set computer (NISC) technology that is developed for fast processor customization. Using several software transformations and hardware customization, we achieved up to 10 times performance improvement, 2 times power reduction, 12.8 times energy reduction, and 3 times area reduction compared to an already-optimized soft-core MIPS implementation
Description Author affiliation: Center for Embedded Syst. Comput., California Univ., Irvine, CA (Gorjiara, B.; Reshadi, M.; Gajski, D.)
ISBN 0780394518
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2006-01-24
Publisher Place Japan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 287.25 kB


Source: IEEE Xplore Digital Library