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Author Bellare, M. ♦ Viet Tung Hoang ♦ Keelveedhi, S. ♦ Rogaway, P.
Sponsorship IEEE Comput. Soc.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2013
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Logic gates ♦ Wires ♦ Cryptography ♦ Protocols ♦ Games ♦ Semantics ♦ Yao's protocol ♦ Garbled circuits ♦ garbling schemes ♦ multiparty computation ♦ random-permutation model ♦ timing study
Abstract We advocate schemes based on fixed-key AES as the best route to highly efficient circuit-garbling. We provide such schemes making only one AES call per garbled-gate evaluation. On the theoretical side, we justify the security of these methods in the random-permutation model, where parties have access to a public random permutation. On the practical side, we provide the Just Garble system, which implements our schemes. Just Garble evaluates moderate-sized garbled-circuits at an amortized cost of 23.2 cycles per gate (7.25 nsec), far faster than any prior reported results.
Description Author affiliation: Dept. of Comput. Sci., Univ. of California, Davis, Davis, CA, USA (Rogaway, P.) || Dept. of Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA (Bellare, M.; Viet Tung Hoang; Keelveedhi, S.)
ISBN 9781467361668
ISSN 10816011
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2013-05-19
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
e-ISBN 9780769549774
Size (in Bytes) 452.24 kB
Page Count 15
Starting Page 478
Ending Page 492


Source: IEEE Xplore Digital Library