Thumbnail
Access Restriction
Subscribed

Author Serpanos, D.N. ♦ Moundrouidou, X. ♦ Gambrili, M.
Sponsorship IEEE Comput. Soc. Tech. Committee on Simulation ♦ IEEE Commun. Soc
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2003
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science ♦ Social sciences ♦ Commerce, communications & transportation ♦ Communications; telecommunication
Subject Keyword Switches ♦ Embedded system ♦ Processor scheduling ♦ Hardware ♦ Embedded software ♦ Packet switching ♦ Performance evaluation ♦ Field programmable gate arrays ♦ System-on-a-chip ♦ Software performance
Abstract We evaluate hardware and software implementations of a centralized and a distributed scheduler for embedded packet switches. The evaluation is performed for embedded system implementation, on a system that includes an FPGA and an embedded, on-chip processor. The results demonstrate that, in contrast to expectations, centralized schedulers provide better performance than distributed ones in hardware implementations. In software implementations for embedded processors, surprisingly, distributed schedulers achieve better performance, due to better management of the processor's limited resources and simpler code.
Description Author affiliation: Dept. of Electr. & Comput. Eng., Patras Univ., Greece (Serpanos, D.N.; Moundrouidou, X.; Gambrili, M.)
ISBN 076951961X
ISSN 15301346
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2003-07-03
Publisher Place Turkey
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 272.73 kB
Page Count 6
Starting Page 541
Ending Page 546


Source: IEEE Xplore Digital Library