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Author Kao, W.H. ♦ Movahed-Ezazi, M.H. ♦ Sabiers, M.L.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1984
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Workstations ♦ Circuit synthesis ♦ CMOS logic circuits ♦ CMOS technology ♦ Graphics ♦ Circuit simulation ♦ Software systems ♦ Logic gates ♦ Logic design ♦ MOS devices ♦ engineering workstation ♦ Transistor sizing ♦ path delay analysis ♦ graphics ♦ computer-aided engineering
Abstract ARIES is a workstation-based, schematic-driven software system for circuit design. It is divided into four major subsystems: SIZING, which generates transistor equivalents for logic gates (NMOS & CMOS technologies) and calculates their sizes (Widths & Lengths); PATHDELAY, which calculates path delays for circuits designed using standard cells; GRAPHICS, a 2-D plotting package that displays results from simulation programs such as SPICE, SUPREM, GEMINI and SUXES; and CANDETOSPICE, which generates, downloads remotely and executes circuit simulation input text files on a VAX 11/780. SIZING, PATHDELAY and CANDE2SPICE use CANDE, a schematic entry graphics editor and database as their front-end. ARIES runs interactively in a multiple overlapping bitmap window (concurrent processing) environment and is completely menu driven. All workstations and VAX 11/780's are connected together via several 10 MB Ethernet LANs.
Description Author affiliation: XEROX Corporation, Electronics Division, El Segundo, CA (Kao, W.H.)
ISBN 0818605421
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1984-06-25
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 538.31 kB
Page Count 7
Starting Page 301
Ending Page 307


Source: IEEE Xplore Digital Library