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Author Lee, D. ♦ Sakuraba, M. ♦ Matsuura, T. ♦ Murota, J. ♦ Tsuchiya, T.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2002
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword MOSFET circuits ♦ Electrodes ♦ Flowcharts ♦ Fabrication ♦ Threshold voltage
Abstract As the feature size of MOSFETs becomes increasingly small, the super self-aligned process is extremely important for the progress of ULSIs. The improvement of carrier mobility in the channel region is also indispensable. It has been reported that the introduction of high-quality Si/sub 1-x/Ge/sub x/ with x/spl ap/0.5 in the channel region drastically improves the pMOSFET performance. In this paper, it is shown that SiGe-channel 0.1-/spl mu/m pMOSFETs with super self-aligned ultra-shallow junction formed by selective in-situ B-doped SiGe chemical vapor deposition (CVD) have been successfully realized. The schematic device structure is described along with the fabrication process flow.
Description Author affiliation: Lab. for Electron. Intelligent Syst., Tohoku Univ., Sendai, Japan (Lee, D.; Sakuraba, M.; Matsuura, T.; Murota, J.)
ISBN 0780373170
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2002-06-24
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 110.58 kB
Page Count 2
Starting Page 83
Ending Page 84


Source: IEEE Xplore Digital Library