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Author Cheongyuen Tsang ♦ Yun Chiu ♦ Vanderhaegen, J. ♦ Hoyos, S. ♦ Chen, C. ♦ Brodersen, R. ♦ Nikolic, B.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2008
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Calibration ♦ Voltage ♦ Pipelines ♦ Operational amplifiers ♦ Transfer functions ♦ Error correction ♦ CMOS digital integrated circuits ♦ CMOS analog integrated circuits ♦ CMOS technology ♦ Digital filters
Abstract A 100 MS/s pipelined ADC is digitally calibrated by a slow SigmaDelta ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411 kHz sinusoidal input, the peak SNDR improves from 28 dB to 59 dB and the SFDR improves from 29 dB to 68 dB. The complete 0.13 mu ADC SoC occupies a die size of 3.7 mm times 4.7 mm, and consumes a total power of 448 mW.
Description Author affiliation: Univ. of California, Berkeley, CA (Cheongyuen Tsang; Chen, C.; Brodersen, R.; Nikolic, B.) || Univ. of Illinois at Urbana-Champaign, Urbana, IL (Yun Chiu) || Texas A&M Univ., College Station, TX (Hoyos, S.) || Bosch Res. & Technol. Center, Palo Alto, CA (Vanderhaegen, J.)
ISBN 9781424420186
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2008-09-21
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 429.71 kB
Page Count 4
Starting Page 301
Ending Page 304


Source: IEEE Xplore Digital Library