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Author Drum, C.M.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1991
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword CMOS technology ♦ Semiconductor device modeling ♦ Integrated circuit modeling ♦ Geometry ♦ Circuit testing ♦ Integrated circuit yield ♦ Solid modeling ♦ Fabrication ♦ Metallization ♦ CMOS integrated circuits
Abstract A mechanistic random-defect yield model has been extended to several CMOS technologies and applied to several types of circuit forms. Inputs to the model include critical geometries for yield analysis obtained from detailed layout analysis, and defect density values obtained from large area test structures, with both inputs being needed for each mechanism. A generally applicable yield model metric is proposed to evaluate the effectiveness of any model. Validation of the present model is given in terms of comparisons of model yields (i) with actual yields and (ii) with yield loss per mechanism as determined by physical analysis of non-functional chips. This model is useful in yield improvement work, since it gives a quantitative analysis of yield loss in terms of particular physical mechanisms. The effects of improving an individual processing step can be quantitatively modeled.<<ETX>>
Description Author affiliation: AT&T Bell Labs., Allentown, PA, USA (Drum, C.M.)
ISBN 0818624574
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1991-11-18
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 140.01 kB
Page Count 3
Starting Page 60
Ending Page 62

Source: IEEE Xplore Digital Library