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Author Yih-Yi Lee ♦ Chien-Lin Chang ♦ Hsiao-Fen Wu ♦ Hsin-Hon Hsieh ♦ Fang, T.C.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2010
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Europe ♦ Fabrication
Abstract Wafer fabrication is the most complex process in Semiconductor Manufacturing Industry that includes the reentrant events, process queue time and lot-tool dispatching. A scheduling approach solves the problem by automated assigning of resources/tools to lots in order to process them in an optimized way. The paper demonstrates a feasible scheduling methodology applying on fabrication optimization through Multi-Direction neighborhood search algorithm (MDNS). By applying on implanter tools, the productivity improved by 2∼3% and reduced inefficient transportation volume around 35%.
Description Author affiliation: Taiwan Semiconductor Manufacturing Company, Ltd, 1-1, Nan-Ke North Rd., Tainan Science Park, Taiwan, 741-44, R.O.C. (Yih-Yi Lee; Chien-Lin Chang; Hsiao-Fen Wu; Hsin-Hon Hsieh; Fang, T.C.)
ISBN 9781457703928
ISSN 1523553X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2010-10-18
Publisher Place Japan
Rights Holder ISSM
Size (in Bytes) 1.68 MB
Page Count 3
Starting Page 1
Ending Page 3


Source: IEEE Xplore Digital Library