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Author Jianhua Liu ♦ Yi Zhu ♦ Haikun Zhu ♦ Chung-Kuan Cheng ♦ Lillis, J.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2007
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Timing ♦ Wire ♦ Capacitance ♦ Computer science ♦ Application specific integrated circuits ♦ High level synthesis ♦ Integer linear programming ♦ Energy consumption ♦ Logic design ♦ Space exploration
Abstract Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures for specific applications. However, the gap between these techniques and back-end designs is increasingly large. In this paper, we propose an integer linear programming method to build minimal-power prefix adders within given timing and area constraints. It counts both gate and wire capacitances in the timing and power models, considers static and dynamic power consumptions, and can handle gate sizing and buffer insertion to improve the performance further. The proposed method is also adaptive for non-uniform arrival time and required time on each bit position. Therefore our method produces the optimum prefix adder for realistic constraints.
Description Author affiliation: Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA (Jianhua Liu)
ISBN 1424406293
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2007-01-23
Publisher Place Japan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 666.62 kB
Page Count 7
Starting Page 609
Ending Page 615


Source: IEEE Xplore Digital Library