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Author Chun-Yao Wang ♦ Shing-Wu Tung ♦ Jing-Yang Jou
Sponsorship IEEE Comput. Soc. Test Technol. Tech. Council
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2001
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Algorithm design and analysis ♦ System-on-a-chip ♦ Fault detection ♦ Time to market ♦ Manufacturing ♦ Cost function ♦ Design methodology ♦ Councils ♦ Testing ♦ Acceleration
Abstract Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC the design verification is a challenge for the system integrator. To reduce the verification complexity, the port order fault (POF) model has been used for verifying core-based designs and the corresponding verification pattern generation has been developed. Here we present an automorphic technique to improve the efficiency of the automatic verification pattern generation (AVPG) for SoC design verification based on POF model. On average, the size, of pattern sets obtained on the ISCAS-85 and MCNC benchmarks are 45% smaller and the run time decreases 16% as compared with the results of AVPG.
Description Author affiliation: Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Chun-Yao Wang)
ISBN 0769513786
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2001-11-19
Publisher Place Japan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 561.88 kB
Page Count 6
Starting Page 431
Ending Page 436

Source: IEEE Xplore Digital Library