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Author Balkan, A.O. ♦ Gang Qu ♦ Vishkin, U.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2008
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Multiprocessor interconnection networks ♦ Parallel processing ♦ Network-on-a-chip ♦ Throughput ♦ Telecommunication traffic ♦ Bandwidth ♦ Delay ♦ Traffic control ♦ Costs ♦ Degradation ♦ Hybrid networks ♦ On-chip networks ♦ Mesh-of-Trees
Abstract Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high through put and low latency at relatively high area cost.In this paper, we introduce a hybrid MoT-BF network that combines MoT network with the area efficient butterfly network. We prove that the hybrid network reduces MoT network's area cost. Cycle-accurate simulation and post-layout results all show that significant area reduction can be achieved with negligible performance degradation, when operating at same clock rate.
Description Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Maryland, College Park, MD (Balkan, A.O.; Gang Qu; Vishkin, U.)
ISBN 9781605581156
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2008-06-08
Publisher Place USA
Rights Holder Association for Computing Machinery, Inc. (ACM)
Size (in Bytes) 328.20 kB
Page Count 6
Starting Page 435
Ending Page 440


Source: IEEE Xplore Digital Library