Access Restriction

Author Renovell, M. ♦ Faure, P. ♦ Portal, J.M. ♦ Figueras, J. ♦ Zorian, Y.
Sponsorship IEEE Comput. Soc. Test Technol. Tech. Council
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2001
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Field programmable gate arrays ♦ Circuit testing ♦ Logic testing ♦ Sequential circuits ♦ Logic circuits ♦ Integrated circuit interconnections ♦ Multiplexing ♦ Programmable logic arrays ♦ Logic programming ♦ Manufacturing
Abstract Proposes a new and original FPGA architecture with testability facilities. It is first demonstrated that classical FPGA architectures do not allow one to efficiently implement sequential circuits with a scan chain. It is consequently proposed to modify the architecture of classical FPGAs in order to create an implicit-scan chain into the FPGA itself called implicit scan FPGA (IS-FPGA). Using this new FPGA architecture, any sequential circuit implemented into the FPGA is 'implicitly scanned'. An original and optimal implementation of the proposed architecture is given with minimum area overhead and absolutely no delay impact. Additionally the technique is transparent for the user as well as for the FPGA mapping tools. Finally, it is demonstrated that the implicit-scan concept allows 'over-scan' of sequential circuits resulting in highly testable circuits.
Description Author affiliation: LIRMM-UM2, Montpellier, France (Renovell, M.)
ISBN 0780371690
ISSN 10893539
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2001-11-01
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 708.11 kB
Page Count 8
Starting Page 924
Ending Page 931

Source: IEEE Xplore Digital Library