Access Restriction

Author Wang Yong-sheng ♦ Xiao Li-yi ♦ Yu Ming-yan ♦ Wang Jin-xiang ♦ Ye Yi-zheng
Sponsorship IEEE Comput. Sci. Test Technol. Tech. Council
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2003
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Boundary scan testing ♦ Self-testing ♦ Integrated circuit testing
Abstract This paper proposes a configurable TAM-Bus, a P1500 compliant Test Access Mechanism (TAM), and the TAM-Bus controller (TAM-controller) that is interfaced with JTAG at chip level of chip. All IP (Intellectual Property) cores' test can be controlled through the TAP under the control of the TAM-controller. The test architecture we presented has been implemented in an industry SoC. The test coverage remains 99.40%. The overhead increases only 0.17% due to TAM. The experiment results demonstrate that the test architecture can offer the solution for testing SoC.
Description Author affiliation: Microelectron. Center, Harbin Inst. of Technol., China (Wang Yong-sheng; Xiao Li-yi; Yu Ming-yan; Wang Jin-xiang; Ye Yi-zheng)
ISBN 0769519512
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2003-11-16
Publisher Place China
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 183.05 kB

Source: IEEE Xplore Digital Library