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Author Wu, E. ♦ Abugharbieh, K. ♦ Banijamali, B. ♦ Ramalingam, S. ♦ Wu, P. ♦ Wyland, C.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2013
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Silicon ♦ Field programmable gate arrays ♦ Wires ♦ Transceivers ♦ Substrates ♦ Integrated optics
Abstract This paper reviews the interconnect and package design of a heterogeneous stacked-silicon FPGA. Up to five dice from two die types are mounted on a passive silicon interposer. A hardware- and software-scalable FPGA family can be created by mixing different combinations of these two die types. The FPGA, inside a low-temperature co-fired ceramic (LTCC) package, consists of two silicon die types - up to three FPGA ICs having a total of seventy-two 13.1-Gb/s transceivers (943.2 Gb/s full-duplex) and up to two GTZ ICs having up to sixteen 28.05-Gb/s transceivers (448.8 Gb/s full-duplex). Two types of interconnects are discussed: those joining the ICs through wires in the silicon interposer, and those connecting the 28-Gb/s transceivers through TSVs in the interposer to the package balls. An end-to-end 28.05-Gb/s channel simulation is discussed in the context of silicon interposer resistivity as well as package material and stack-up. In addition, this paper reviews 3D thermal-mechanical analysis confirming the reliability of heterogeneous stacked silicon.
Description Author affiliation: Xilinx, Inc., San Jose, CA, USA (Wu, E.; Abugharbieh, K.; Banijamali, B.; Ramalingam, S.; Wu, P.; Wyland, C.)
ISBN 9781467361460
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2013-09-22
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 1.35 MB
Page Count 8
Starting Page 1
Ending Page 8


Source: IEEE Xplore Digital Library