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Author Akioka, T. ♦ Hiraishi, A. ♦ Yamauchi, T. ♦ Yokoyama, Y. ♦ Takahashi, S. ♦ Iwamura, M. ♦ Kobayashi, Y. ♦ Ide, A. ♦ Gotou, N. ♦ Onozawa, K. ♦ Uchida, H.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1990
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword BiCMOS integrated circuits ♦ Random access memory ♦ Decoding ♦ Pulse amplifiers ♦ Capacitance ♦ Driver circuits ♦ Cities and towns ♦ Pulse circuits ♦ Delay effects ♦ Laboratories
Abstract A 6-ns 64K*4-b BiCMOS, transistor-transistor logic (TTL)-I/O SRAM has been developed. Fast access time is due to the combination of innovative circuits and a double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The novel circuits include a reduced-stage BiCMOS decoder and a current-sense-type address transition detection circuit. The chip size is 4.25 mm*10 mm. Simulated internal delay time components of a critical path of the decoder are shown. Address access time is 6 ns at T/sub a/=25 degrees C, V/sub CC/=5 V with a 30 pF load connected to the common I/O node.<<ETX>>
Description Author affiliation: Hitachi Ltd., Ibaraki, Japan (Akioka, T.; Hiraishi, A.; Yamauchi, T.; Yokoyama, Y.; Takahashi, S.; Iwamura, M.; Kobayashi, Y.)
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1990-05-13
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 211.34 kB


Source: IEEE Xplore Digital Library