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Author Koch, A.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1996
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Compaction ♦ Field programmable gate arrays ♦ Logic ♦ Delay ♦ Permission ♦ Integrated circuit synthesis ♦ Runtime ♦ Digital signal processing ♦ History ♦ Very large scale integration
Abstract When relying on module generators to implement regular datapaths on FPGAs, the coarse granularity of FPGA cells can lead to area and delay inefficiencies. We present a method to alleviate these problems by compacting adjacent modules using structure extraction, local logic synthesis, and cell replacement. The regular datapath structure is exploited and preserved, achieving faster layouts after shorter tool run-times.
Description Author affiliation: Dept. for Integrated Circuit Design, Tech. Univ. Braunschweig, Germany (Koch, A.)
ISBN 0780332946
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1996-06-03
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 822.42 kB
Page Count 6
Starting Page 471
Ending Page 476


Source: IEEE Xplore Digital Library