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Author Gemmeke, T. ♦ Sabry, M.M. ♦ Stuijt, J. ♦ Raghavan, P. ♦ Catthoor, F. ♦ Atienza, D.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2014
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Oceans ♦ Voltage measurement ♦ Error correction codes ♦ Random access memory ♦ Memory management ♦ Power demand ♦ System-on-chip ♦ memories ♦ Near-threshold computing
Abstract This paper focuses on a review of state-of-the-art memory designs and new design methods for near-threshold computing (NTC). In particular, it presents new ways to design reliable low-voltage NTC memories cost-effectively by reusing available cell libraries, or by adding a digital wrapper around existing commercially available memories. The approach is based on modeling at system level supported by silicon measurement on a test chip in a 40nm low-power processing technology. Advanced monitoring, control and run-time error mitigation schemes enable the operation of these memories at the same optimal $near-V_{t}$ voltage level as the digital logic. Reliability degradation is thus overcome and this opens the way to solve the memory bottleneck in NTC systems. Starting from the available 40 nm silicon measurements, the analysis is extended to future 14 and 10 nm technology nodes.
Description Author affiliation: Holst-Centre, imec, Eindhoven, Netherlands (Gemmeke, T.; Stuijt, J.) || imec Leuven, Leuven, Belgium (Raghavan, P.; Catthoor, F.) || ESL-EPFL, Lausanne, Switzerland (Sabry, M.M.; Atienza, D.)
ISBN 9783981537024
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2014-03-24
Publisher Place Germany
Rights Holder European Design Automation Association (EDAA)
Size (in Bytes) 669.20 kB
Page Count 6
Starting Page 1
Ending Page 6

Source: IEEE Xplore Digital Library