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Author Das, D. ♦ Touba, N.A.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2000
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Circuit testing ♦ Logic testing ♦ Built-in self-test ♦ Circuit faults ♦ System testing ♦ Costs ♦ Logic design ♦ Automatic testing ♦ Manufacturing ♦ Automatic test pattern generation
Abstract A common approach for large industrial designs is to use logic built-in self-test (LBIST) followed by test data from an external tester. Because the fault coverage with LBIST alone is not sufficient, there is a need to top-up the fault coverage with additional deterministic test patterns from an external tester. This paper proposes a technique of combining LBIST and deterministic ATPG to form "hybrid test patterns" which merge pseudo-random and deterministic test data. Experiments have been done on the Motorola PowerPC/sup TM/ microprocessor core to study the proposed hybrid test patterns. Hybrid test patterns provide several advantages: (1) can be applied using STUMPS architecture (Bardell, 82) with a minor modification, (2) significantly reduce external test data stored in tester memory, (3) reduce the number of pseudorandom patterns by orders of magnitude, thus addressing power issues.
Description Author affiliation: Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA (Das, D.)
ISBN 0780365461
ISSN 10893539
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2000-10-05
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 712.41 kB
Page Count 8
Starting Page 115
Ending Page 122


Source: IEEE Xplore Digital Library