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Author Shih-Hsu Huang ♦ Chia-Ming Chang ♦ Yow-Tyng Nieh
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2006
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Clocks ♦ Processor scheduling ♦ Circuits ♦ Minimization ♦ Scheduling algorithm ♦ Delay ♦ Intersymbol interference ♦ Polynomials ♦ Integer linear programming ♦ Cost function
Abstract Given several specific clocking domains, the peak current minimization problem can be formulated as a 0-1 integer linear program. However, if the number of binary variables is large, the run time is unacceptable. In this paper, we study the reduction of this high computational expense. Our approach includes the following two aspects. First, we derive the ASAP schedule and the ALAP schedule to prune the redundancies without sacrificing the exactness (optimality) of the solution. Second, we propose a zone-based scheduling algorithm to solve a large circuit heuristic ally.
Description Author affiliation: Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan (Shih-Hsu Huang; Chia-Ming Chang; Yow-Tyng Nieh)
ISBN 0780394518
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2006-01-24
Publisher Place Japan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 252.81 kB

Source: IEEE Xplore Digital Library