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Author Kobayashi, M. ♦ Makita, T. ♦ Matsui, S. ♦ Koyama, M. ♦ Fujii, N. ♦ Hatono, I. ♦ Ueda, K.
Sponsorship IEEE Electron Devices Soc.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2001
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Fluctuations ♦ Production ♦ Process planning ♦ Throughput ♦ Semiconductor device manufacture ♦ Manufacturing systems ♦ System-on-a-chip ♦ Research and development ♦ Marine vehicles ♦ Manufacturing processes
Abstract Floor layout to realize short accumulated distance of product and high throughput is required. Currently, however, it is very difficult and takes a very long time to optimize floor planning in a wafer process, because of complex process flow. In this paper we propose a new method of floor planning based on self-organization to solve these problems. We verify the validity of applying this method to semiconductor manufacturing. Self-organization method can generate a floor layout plan autonomously. In particular, potential field modeling method can describe simulation models in a simple way, because it controls all entities in the same method. The results of simulation indicate that the proposed method can provide the layout plan with short accumulated distance of product without requiring considerable labor and time.
Description Author affiliation: Sony Corp., Japan (Kobayashi, M.)
ISBN 0780367316
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2001-10-08
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 386.86 kB
Page Count 4
Starting Page 381
Ending Page 384


Source: IEEE Xplore Digital Library