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Author Wujie Wen ♦ Yaojun Zhang ♦ Mengjie Mao ♦ Yiran Chen
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2014
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Error analysis ♦ Resistance ♦ Computer architecture ♦ Reliability ♦ Microprocessors ♦ Programming ♦ Error correction codes ♦ Performance ♦ STT-RAM ♦ Multi-Level Cell ♦ Reliability
Abstract Multi-level Cell Spin-Transfer Torque Random AccessMemory (MLC STT-RAM) is a promising nonvolatile memory technology for high-capacity and high-performance applications. However, the reliability concerns and the complicated access mechanism greatly hinder the application of MLC STT-RAM. In this work, we develop a holistic solution set, namely, state-restrict MLC STT-RAM (SR-MLC STT-RAM) to improve the data integrity and performance of MLC STT-RAM with the minimized information density degradation. Three techniques: state restriction (StatRes), error pattern removal (ErrPR), and ternary coding (TerCode) are proposed at circuit level to reduce the read and write errors of MLC STT-RAMcells. State pre-recovery (PreREC) technique is also developed at architecture level to improve the access performance of SR-MLC STT-RAM by eliminating unnecessary two-step write operations. Our simulations show that compared to conventional MLC STT-RAM, SR-MLC STT-RAM can enhance the write and read reliability of memory cells by 10 - 10000×, allowing the application of simple error correction code schemes. Compared to single-level-cell (SLC) STT-RAM, SR-MLC STT-RAM based cache design can boost the system performance by 6.2% on average by leveraging the increased cache capacity at the same area and the improved write latency.
Description Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Pittsburgh, Pittsburgh, PA, USA (Wujie Wen; Yaojun Zhang; Mengjie Mao; Yiran Chen)
ISBN 9781479930173
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2014-06-01
Publisher Place USA
Rights Holder Association for Computing Machinery, Inc. (ACM)
Size (in Bytes) 441.69 kB
Page Count 6
Starting Page 1
Ending Page 6


Source: IEEE Xplore Digital Library