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Author Lan, S. ♦ Ziv, A. ♦ El Gamal, A.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1994
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Routing ♦ Wires ♦ Switches ♦ Pins ♦ Costs ♦ Field programmable gate arrays ♦ Wiring ♦ Simulated annealing ♦ Random access memory ♦ Joining processes
Abstract Placement and routing heuristics for a Field Programmable Multi-Chip Module (FPMCM) are presented. The placement is done in three phases; partitioning, chip assignment and iterative improvement. The routing is done in two phases; global routing followed by detailed routing. Detailed routing involves new channel routing problems denoted by Exact Segmented Channel Routing (ESCR) and K-ESCR. A very fast K-ESCR heuristic is described. Experimental results show that the placement heuristic achieves high gate utilization, and that the K-ESCR heuristic performs surprisingly well over wide range of channel sizes.
Description Author affiliation: Information Systems Laboratory, Stanford University, Stanford, CA (Lan, S.)
ISBN 0897916530
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1994-06-06
Publisher Place USA
Rights Holder Association for Computing Machinery, Inc. (ACM)
Size (in Bytes) 209.71 kB
Page Count 6
Starting Page 295
Ending Page 300


Source: IEEE Xplore Digital Library