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Author Cardarilli, G.C. ♦ Lojacono, R. ♦ Salerno, M. ♦ Sargeni, F.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1992
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Digital filters ♦ Arithmetic ♦ Finite impulse response filter ♦ Parallel processing ♦ Equations ♦ Very large scale integration ♦ Delay ♦ Clocks ♦ CMOS technology ♦ Pipeline processing
Abstract VLSI realization of single chip IIR digital filters is described. In order to improve speed performance, the arithmetic operations are implemented in parallel, on the basis of residue number system technique. The main feature of the realization is that the delay time related than 100 nsec, so that filters with more than 10 MHz clock rate cane be obtained. Even though an 8 bit wordlength is used for signals, the overall accuracy of the filter is far better than that of an 8 bit conventional realization, because of the favourable properties of the finite arithmetic which makes most inner operations free of arithmetic errors. The final layout has been realized with 1.5 micron CMOS standard cell technology.<<ETX>>
Description Author affiliation: Dept. of Electron. Eng., Rome Univ., Italy (Cardarilli, G.C.; Lojacono, R.; Salerno, M.; Sargeni, F.)
ISBN 0818628456
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1992-06-01
Publisher Place France
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 287.91 kB
Page Count 4
Starting Page 314
Ending Page 317


Source: IEEE Xplore Digital Library