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Author Yang Jin ♦ Hong Wang ♦ Zhengliang Lv ♦ Shiyuan Yang
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2010
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Circuit testing ♦ Automatic testing ♦ System testing ♦ Costs ♦ Design for testability ♦ Hardware ♦ Design automation ♦ Pressing ♦ Energy consumption ♦ Signal generators
Abstract Testing of mixed-signal SoCs becomes one of the pressing challenges due to enormous test cost including ATE expenses, design for test (DFT) hardware overhead and test application time. Prior researches focus mainly on minimizing test cost for digital SoCs under the constraint of ATE test resources and power consumption. A self-hold analog test wrapper design and pipelined parallel test manner are proposed in this paper to realize both core-level and system-level parallel test for low to mid-frequency analog cores in mixed-signal SoCs.
Description Author affiliation: Department of Automation, Tsinghua University, Beijing, China, 100084 (Yang Jin; Hong Wang; Zhengliang Lv; Shiyuan Yang)
ISBN 9781424458349
ISSN 15301877
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2010-05-24
Publisher Place Czech Republic
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
e-ISBN 9781424458356
Size (in Bytes) 209.44 kB
Page Count 1
Starting Page 256
Ending Page 256


Source: IEEE Xplore Digital Library