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Author Canesin, C.A. ♦ Goncalves, F.A.S.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2005
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Rectifiers ♦ Digital control ♦ Field programmable gate arrays ♦ Electromagnetic interference ♦ Reactive power ♦ Zero current switching ♦ Diodes ♦ Voltage control ♦ Switches ♦ Magnetic losses
Abstract This paper presents a 2 kW single-phase high power factor boost rectifier with four cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by field programmable gate array (FPGA). The soft-switching technique is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the interleaving technique, the rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for four interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a 2 kW implemented prototype with four interleaved cells, 400 V nominal output voltage and 220 $V_{rms}$ nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device
Description Author affiliation: Dept. of Electr. Eng., Sao Paulo State Univ. (Canesin, C.A.; Goncalves, F.A.S.)
ISBN 0780390334
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2005-06-16
Publisher Place Brazil
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 1.05 MB
Page Count 6
Starting Page 513
Ending Page 518

Source: IEEE Xplore Digital Library