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Author Schaumont, P. ♦ Verbauwhede, I.
Sponsorship EDAA, EDA Consortium, IEEE Comput. Soc. TTTC ♦ IEEE Comput. Soc. DATC ♦ ECSI ♦ ACM/SIGDA ♦ RAS
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2004
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Hardware ♦ Decoding ♦ Cryptography ♦ Coprocessors ♦ Computer languages ♦ Embedded software ♦ Design automation ♦ Automatic testing ♦ Software testing ♦ System testing
Abstract We present a technique to improve the efficiency of hardware-software cosimulation, using design information known at simulator compile-time. The generic term for such optimization is partial evaluation. Our contribution is that we apply the optimization transparently to the user, and at multiple abstraction levels in the simulation. We use the technique to create an interactive codesign environment, and evaluate it on several designs including an AES encryption coprocessor and a Viterbi decoder, and for several instruction-set simulators. Compared to SystemC-based cosimulation, we achieve comparable cosimulation performance at only a fraction of the model-build time.
Description Author affiliation: Dept. of Electr. Eng., Califonia Univ., Los Angeles, CA, USA (Schaumont, P.; Verbauwhede, I.)
ISBN 0769520855
ISSN 15301591
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2004-02-16
Publisher Place France
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 233.96 kB
Page Count 6
Starting Page 642
Ending Page 647


Source: IEEE Xplore Digital Library