Access Restriction

Author Zude Zhou ♦ Songlin Cheng ♦ Quan Liu
Sponsorship IEEE ♦ ICIC Int. ♦ National Natural Sci. Found. of China ♦ Beijing Jiaotong Univ. ♦ Kaosiung Univ. of Appl. Sci
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2006
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Data acquisition ♦ Communication system control ♦ Random access memory ♦ Bridge circuits ♦ DRAM chips ♦ Throughput ♦ SDRAM ♦ Hardware design languages ♦ Field programmable gate arrays ♦ Clocks
Abstract DDR SDRAM (double data rate synchronously dynamic RAM) controller is discussed in this paper. The principle and commands of FPGA-based DDR SDRAM controller are detailed. The R/W control of DDR SDRAM is realized through Verilog HDL, and this controller is applied into 400 MHz single channel high-speed, high-precision and large-capacity data acquisition board
Description Author affiliation: Sch. of Inf. Eng., Wuhan Univ. of Technol. (Zude Zhou; Songlin Cheng; Quan Liu)
ISBN 0769526160
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2006-08-30
Publisher Place China
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 199.94 kB
Page Count 4
Starting Page 611
Ending Page 614

Source: IEEE Xplore Digital Library