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Author Ganapathy, G. ♦ Narayan, R. ♦ Jorden, C. ♦ Ming Wang ♦ Nishimura, J.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1996
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Hardware ♦ Emulation ♦ Microprocessors ♦ Computer architecture ♦ Field programmable gate arrays ♦ Permission ♦ Logic ♦ Postal services ♦ Transistors ♦ Silicon
Abstract The K5 microprocessor is a 4 Million transistor superscalar, X86 microprocessor. The K5 microprocessor is an AMD original design, verifying compatibility with the existing X86 architecture and software is crucial to its success in the market place. The X86 architecture has been constantly evolving over several years without any published specification. The primary mechanism for functional design verification of an X86 processor is simulation. The ability to execute a good sample set of the X86 software base on a model of the processor architecture before tapeout is key to achieving very high confidence first silicon. The Quickturn Hardware Emulation system allows us to map a model of the design onto hardware resources and execute it at high speeds. In this paper we present the emulation methodology that was jointly developed for K5 and applied successfully to meet our functional verification goals.
Description Author affiliation: Adv. Micro Devices Inc., Austin, TX, USA (Ganapathy, G.)
ISBN 0780332946
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1996-06-03
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 431.40 kB
Page Count 4
Starting Page 315
Ending Page 318


Source: IEEE Xplore Digital Library