Access Restriction

Author Yonghwan Lee ♦ Wookyung Jeong ♦ Sangjun Ahn ♦ Yongsurk Lee
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1997
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Technical Activities Guide -TAG ♦ Cache memory ♦ Microprocessors ♦ Frequency ♦ Circuit simulation ♦ Area measurement ♦ Velocity measurement ♦ Semiconductor device measurement ♦ Integrated circuit measurements ♦ Very large scale integration
Abstract In this paper, we propose a shared tag memory through which both TLB and cache memory can be accessed. The shared tag architecture reduces the area of conventional cache tag memory and also improves the speed of cache system. To validate the proposed architecture, we conducted trace-driven simulations and measured the area and speed based on VLSI circuits.
Description Author affiliation: Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea (Yonghwan Lee)
ISBN 0780338049
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1997-10-07
Publisher Place Romania
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 400.93 kB
Page Count 4
Starting Page 77
Ending Page 80

Source: IEEE Xplore Digital Library