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Author Chunhua Yao ♦ Saluja, K.K. ♦ Ramanathan, P.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2009
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Processor scheduling ♦ System testing ♦ Scheduling algorithm ♦ Energy consumption ♦ Temperature ♦ Computational modeling ♦ Logic testing ♦ Thermal engineering ♦ Quantum computing ♦ Costs ♦ Superposition ♦ SoC Test ♦ Test scheduling ♦ Test partition ♦ Thermal simulation
Abstract For core-based System-on-Chip (SoC) testing, conventional power-constrained test scheduling methods do not guarantee a thermal-safe solution. Also, most of the test scheduling schemes make poor assumptions about power consumption. In deep submicron era, leakage power and wake-up power consumption can not be neglected. In this paper, we propose a partition based thermal-aware test scheduling algorithm with more realistic assumptions of recent SoCs. In our test scheduling algorithm, each test is partitioned and the earliest starting time of each partition is searched. To reduce the execution time of thermal simulation, we also exploit superposition principle to compute the power and thermal profile rapidly and accurately. We apply our test scheduling algorithm to ITC’02 SoC benchmarks and the results show improvements in the total test time over scheduling schemes without partitioning.
ISBN 9780769538648
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2009-11-23
Publisher Place Taiwan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 478.00 kB
Page Count 6
Starting Page 281
Ending Page 286

Source: IEEE Xplore Digital Library