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Author Cliff, R. ♦ Ahanin, B. ♦ Cope, L.T. ♦ Heile, F. ♦ Ho, R. ♦ Huang, J. ♦ Lytle, C. ♦ Mashruwala, S. ♦ Pedersen, B. ♦ Raman, R. ♦ Reddy, S. ♦ Singhal, V. ♦ Sung, C.K. ♦ Veenstra, K. ♦ Gupta, A.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1993
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Programmable logic devices ♦ Integrated circuit interconnections ♦ Logic arrays ♦ Clocks ♦ Logic design ♦ System performance ♦ Table lookup ♦ Pins ♦ Counting circuits ♦ Application specific integrated circuits
Abstract A novel architecture called FLEX (flexible logic element matrix) has been designed which supports high logic densities up to 24,000 gates, maximizing overall system performance in a user design. This has been accomplished through a dual granularity approach and a global interconnect strategy. The dual granularity and global interconnect approach has succeeded in supporting both short nets and long nets for maximum performance.
Description Author affiliation: Alter Corp., San Jose, CA, USA (Cliff, R.)
ISBN 0780308263
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1993-05-09
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 475.39 kB

Source: IEEE Xplore Digital Library