Thumbnail
Access Restriction
Subscribed

Author Cilardo, A.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2009
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Adders ♦ Circuits ♦ Computer architecture ♦ Heart ♦ Microprocessors ♦ Arithmetic ♦ Added delay ♦ Frequency ♦ Error correction ♦ Clocks
Abstract Existing architectures for speculative addition are all based on the assumption that operands have uniformly distributed bits, which is rarely verified in real applications. As a consequence, they may be disadvantageous for real-world workloads, although in principle faster than standard adders. To address this limitation, we introduce a new architecture based on an innovative technique for speculative global carry evaluation. The proposed architecture solves the main drawback of existing schemes and, evaluated on real-world benchmarks, it exhibits an interesting performance improvement with respect to both standard adders and alternative architectures for speculative addition.
Description Author affiliation: Università degli Studi di Napoli Federico II, Dipartimento di Informatica e Sistemistica, Via Claudio 21, 80125, Italy (Cilardo, A.)
ISBN 9781424437818
ISSN 15301591
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2009-04-20
Publisher Place France
Rights Holder European Design Automation Association (EDAA)
Size (in Bytes) 275.45 kB
Page Count 6
Starting Page 664
Ending Page 669


Source: IEEE Xplore Digital Library