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Author Nowak, E.J. ♦ Ludwig, T. ♦ Aller, I. ♦ Kedzierski, J. ♦ Leong, M. ♦ Rainey, B. ♦ Breitwisch, M. ♦ Gemhoefer, V. ♦ Keinert, J. ♦ Fried, D.M.
Sponsorship IEEE Solid-State Circuits Soc. ♦ IEEE Electron Devices Soc
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2003
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Double-gate FETs ♦ CMOS technology ♦ Subthreshold current ♦ Ultra large scale integration ♦ FinFETs ♦ Frequency ♦ Clocks ♦ Microelectronics ♦ Fabrication ♦ CMOS process
Abstract Exponential growth in leakage power density with physical scaling is driving ULSI technology towards innovative device architectures. Double-gate CMOS (DGCMOS), achieved through use of the Delta Device (D.Hisamoto et al, IEDM 1989, p.833-836), or FinFET (X.Huang et al, IEDM 1999, p.67-70), provides both a tactical solution to the gate-leakage challenge and a strategic scaling advantage. FinFET fabrication is very close to that of the conventional CMOS process, with only minor disruptions, yielding the potential for a rapid deployment to manufacturing. Planar circuit designs have been converted to FinFET-DGCMOS without disruption to physical area.
Description Author affiliation: IBM Syst. Group, IBM Microelectron. Div., Essex Junction, VT, USA (Nowak, E.J.)
ISBN 0780378423
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2003-09-24
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 296.78 kB
Page Count 4
Starting Page 339
Ending Page 342

Source: IEEE Xplore Digital Library