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Author Zordan, L. B. ♦ Bosio, A. ♦ Dilillo, L. ♦ Girard, P. ♦ Todri, A. ♦ Virazel, A. ♦ Badereddine, N.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2013
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Voltage control ♦ Regulators ♦ Random access memory ♦ Arrays ♦ Transistors ♦ Power demand ♦ Resistance ♦ memory test ♦ SRAM ♦ low-power design ♦ test algorithm
Abstract Low-power SRAMs embed mechanisms for reducing static power consumption. When the SRAM is not accessed during a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cells as low as possible without data loss. Thus, faulty-free behavior of the voltage regulator is crucial for ensuring data retention in core-cells when the SRAM is in low-power mode. This paper investigates the root cause of data retention faults due to voltage regulator malfunctions. This analysis is done under realistic conditions (i.e., industrial core-cells affected by process variations). Based on this analysis, we propose an efficient test flow for detecting data retention faults in low-power SRAMs.
Description Author affiliation: Intel Mobile Communications, 2600, route des Crêtes - 06560 Sophia-Antipolis, France (Badereddine, N.) || LIRMM - Université Montpellier II / CNRS, 161, rue Ada - 34095 Cedex 5, France (Zordan, L. B.; Bosio, A.; Dilillo, L.; Girard, P.; Todri, A.; Virazel, A.)
ISBN 9781467350716
ISSN 15301591
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2013-03-18
Publisher Place France
Rights Holder European Design Automation Association (EDAA)
e-ISBN 9783981537000
Size (in Bytes) 1.01 MB
Page Count 6
Starting Page 442
Ending Page 447

Source: IEEE Xplore Digital Library