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Author Blanton, S.
Sponsorship IEEE Comput. Soc.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2014
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Abstract Since yield is not 100%, the main objective of test has and continues to be screening out bad ICs. Today, however, test is being used to provide valuable information about failing chips, answering questions about whether the design, the fabrication process or some combination of the two is responsible for failure. The information extracted is, ideally, used to improve design, fabrication and even test itself. In this talk, an overview of research in the Carnegie Mellon Advanced Chip Testing Laboratory in this area will be described with particular emphasis on one methodology that focuses on measuring the effectiveness of any fault model or test metric using normally-available test data. Experiment results from manufactured chips from both IDMs and chip-design houses will be used to illustrate the potential of this approach.
ISBN 9781479960309
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Publisher Date 2014-11-16
Publisher Place China
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 183.83 kB

Source: IEEE Xplore Digital Library