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Author Vandenbussche, J. ♦ Uyttenhove, K. ♦ Lauwers, E. ♦ Steyaert, M. ♦ Gielen, G.
Sponsorship IEEE Solid State Circuits Soc. ♦ Electron Devices Soc
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2002
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Preamplifiers ♦ Capacitance ♦ CMOS process ♦ Semiconductor device measurement ♦ Power supplies ♦ Frequency measurement ♦ Parallel processing ♦ Energy consumption ♦ Signal resolution ♦ Rail to rail outputs
Abstract A 8-bit 200MS/s 4-2 interpolating A/D converter is presented. A novel input stage was developed to enhance the dynamic performance. Static performance is enhanced using the averaging technique. The chip has been fabricated in a standard 0.35 /spl mu/m CMOS process. An INL/DNL of 0.95/0.8 LSB was measured. An SNR figure of 44.3 dB was achieved at low frequencies: for a 30 MHz input signal an SNR figure of 43 dB was measured.
Description Author affiliation: Dept. of Electr. Eng., Katholieke Univ., Leuven, Heverlee, Belgium (Vandenbussche, J.; Uyttenhove, K.; Lauwers, E.; Steyaert, M.; Gielen, G.)
ISBN 0780372506
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2002-05-15
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 407.85 kB
Page Count 4
Starting Page 445
Ending Page 448


Source: IEEE Xplore Digital Library