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Author Bahl, S. ♦ Mattiuzzo, R. ♦ Khullar, S. ♦ Garg, A. ♦ Graniello, S. ♦ Abdel-Hafez, K.S. ♦ Talluto, S.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2011
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Clocks ♦ Automatic test pattern generation ♦ Switches ♦ Power demand ♦ Logic gates ♦ Flip-flops ♦ Vectors ♦ switching activity ♦ capture power reduction ♦ on-chip clock controller ♦ vectorless power calculation
Abstract Power consumption during test can be significantly higher than during normal functional mode. This paper presents a low power Automated Test Pattern Generation (ATPG) flow for managing capture power in today's power critical designs. It introduces a novel method for sequentially enabling the on-chip clock controllers to generate accurate low power ATPG patterns respecting the power specifications of the design. The effectiveness of the method is demonstrated on several industrial designs that show up power issues during test mode.
Description Author affiliation: Technology Research and Development, STMicroelectronics India (Bahl, S.; Khullar, S.; Garg, A.) || Synopsys Inc., 700 East Middlefield Road, Mountain View, CA 94043 (Abdel-Hafez, K.S.; Talluto, S.) || Technology Research and Development, STMicroelectronics Italy (Mattiuzzo, R.; Graniello, S.)
ISBN 9781457701535
ISSN 10893539
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2011-09-20
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
e-ISBN 9781457701528
Size (in Bytes) 1.16 MB
Page Count 10
Starting Page 1
Ending Page 10

Source: IEEE Xplore Digital Library