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Author Basturkmen, N.Z. ♦ Reddy, S.M. ♦ Pomeranz, I.
Sponsorship IEEE Comput. Soc. Test Technol. Tech. Council ♦ IEEE Philadelphia Sect
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2002
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Built-in self-test ♦ Circuit testing ♦ Circuit faults ♦ Test pattern generators ♦ Hardware ♦ Fault detection ♦ Integrated circuit testing ♦ Costs ♦ Cities and towns ♦ Sun
Abstract Proposes a new pseudo-random pattern generator for scan circuits. The proposed generator uses Markov sources to capture spatial correlations between consecutive bits inside a scan chain as defined by weight sets generated using a weighted random pattern testing method. The weight set generation is based on the analysis of deterministic test sets. The BIST scheme that uses the proposed pattern generator iteratively modifies the generator behavior to obtain a full fault coverage. Experiments conducted on large benchmark circuits demonstrate that the proposed BIST methodology can achieve full fault coverage with a small number of tests and a small hardware overhead.
Description Author affiliation: Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA (Basturkmen, N.Z.; Reddy, S.M.)
ISBN 0780375424
ISSN 10893539
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2002-10-10
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 574.42 kB
Page Count 9
Starting Page 1013
Ending Page 1021

Source: IEEE Xplore Digital Library