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Author Knopf, R. ♦ Trischler, E.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1989
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Circuit testing ♦ Clocks ♦ Sequential analysis ♦ Timing ♦ Delay ♦ Law ♦ Legal factors ♦ Computer aided engineering ♦ Logic ♦ Design for testability
Abstract The hierarchical design for testability (DFT) rule checker Cerberus has been developed to handle hierarchical circuits supporting a variety of scan structures with different types of scannable storage devices. Cerberus utilizes a general approach to testability rule checking and is part of a computer-aided engineering system to integrate design and test. Cerberus consists of the following components: an extractor to provide a levelized directed graph representation from a circuit netlist, a preprocessor to provide acyclic graphs and for topological sorting of circuit nodes, a rule checker nucleus to perform the DFT verification process hierarchically, and a protocol generator to output the rule-checker results in a user-friendly representation.<<ETX>>
Description Author affiliation: Siemens AG, Munich, West Germany (Knopf, R.; Trischler, E.)
ISBN 0818619376
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1989-04-12
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 316.03 kB
Page Count 5
Starting Page 58
Ending Page 62


Source: IEEE Xplore Digital Library