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Author Rusu, A. ♦ Ravariu, C. ♦ Rusu, A. ♦ Dobrescu, D. ♦ Cozma, D.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2010
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Logic gates ♦ Junctions ♦ Semiconductor process modeling ♦ Doping ♦ Electric breakdown ♦ Breakdown voltage ♦ Substrates ♦ equivalent circuit ♦ unconventional MOS device ♦ gated diode breakdown ♦ simulations
Abstract This paper presents the simulation results of the gate-controlled diode, working in the analog regime. The aim of the paper is to find the device macromodel that provides an optimum linearity of the junction voltage versus the gate voltage, at a given current. The lateral pn junction is simulated in the breakdown regime and the gate voltage biases the MOS capacitor in deep depletion. Finally, linearity under 1% was accomplished, being in agreement with the theory. An equivalent circuit was developed according to these simulations in order to be implemented in Spice like programs.
Description Author affiliation: “Politehnica” University of Bucharest, Faculty of Electronics Telecommunications and Information Technology, Romania (Rusu, A.; Ravariu, C.; Rusu, A.; Dobrescu, D.; Cozma, D.)
ISBN 9781424457830
ISSN 1545827X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2010-10-11
Publisher Place Romania
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
e-ISBN 9781424457823
Size (in Bytes) 1.52 MB
Page Count 4
Starting Page 419
Ending Page 422

Source: IEEE Xplore Digital Library