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Author Beck, M. ♦ Barondeau, O. ♦ Kaibel, M. ♦ Poehl, F. ♦ Xijiang Lin ♦ Press, R.
Sponsorship European Design and Autom. Assoc. ♦ EDA Consortium ♦ IEEE Comput. Soc. TTTC, IEEE Comput. Soc. DATC, ECSI, ACM SIGDA, RAS
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2005
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Logic testing ♦ Logic design ♦ Clocks ♦ Delay ♦ Circuit testing ♦ Automatic testing ♦ Circuit faults ♦ Automatic test pattern generation ♦ Production ♦ System-on-a-chip
Abstract This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.
Description Author affiliation: Infineon Technol. AG, Munich, Germany (Beck, M.; Barondeau, O.; Kaibel, M.; Poehl, F.)
ISBN 0769522882
ISSN 15301591
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2005-03-07
Publisher Place Germany
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 198.18 kB
Page Count 6
Starting Page 56
Ending Page 61


Source: IEEE Xplore Digital Library