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Author Xijiang Lin ♦ Kun-Han Tsai ♦ Chen Wang ♦ Kassab, M. ♦ Rajski, J. ♦ Kobayashi, T. ♦ Klingenberg, R. ♦ Sato, Y. ♦ Hamada, S. ♦ Aikyo, T.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2006
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Automatic test pattern generation ♦ Circuit faults ♦ Circuit testing ♦ Fault detection ♦ Added delay ♦ Timing ♦ Robustness ♦ Logic circuits ♦ Manufacturing ♦ Frequency
Abstract In this paper, a new ATPG methodology is proposed to improve the quality of test sets generated for detecting delay defects. This is achieved by integrating timing information, e.g. from standard delay format (SDF) files, into the ATPG tool. The timing information is used to guide the test generator to detect faults through the longest paths in order to improve the ability to detect small delay detects. To avoid propagating faults through similar paths repeatedly, a weighted random method is proposed to improve the path coverage during test generation. During fault simulation, a new fault-dropping criterion, named dropping based on slack margin (DSM), is proposed to facilitate the trade-off between the test set quality and the test pattern count. The quality of the generated test set is measured by two metrics: delay test coverage and SDQL. The experimental results show that significant test quality improvement is achieved when applying timing-aware ATPG with DSM to industrial designs
Description Author affiliation: Mentor Graphics Corp., Wilsonville, OR (Xijiang Lin; Kun-Han Tsai; Chen Wang; Kassab, M.; Rajski, J.; Kobayashi, T.; Klingenberg, R.)
ISBN 0769526284
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2006-11-20
Publisher Place Japan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 248.82 kB
Page Count 8
Starting Page 139
Ending Page 146

Source: IEEE Xplore Digital Library