Access Restriction

Author Kimoto, M. ♦ Shimizu, H. ♦ Ito, Y. ♦ Kohno, K. ♦ Ikeda, M. ♦ Deguchi, T. ♦ Fukuda, N. ♦ Ueda, K. ♦ Harada, S. ♦ Kubota, K.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1989
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Abstract The authors have developed an ECL (emitter-coupled logic) 64-kb RAM with 3680-gate logic gate array LSI using bipolar technology. The address access time is 1.4 ns (typical), clock access time is 1.8 ns (typical), and the propagation delay of the logic rate is 85 ps. The chip is 13.5 $mm^{2}$ in area and packaged in a 462-pin grid array
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1989-05-15
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 328.42 kB

Source: IEEE Xplore Digital Library