Thumbnail
Access Restriction
Subscribed

Author Acero, C. ♦ Feltham, D. ♦ Hapke, F. ♦ Moghaddam, E. ♦ Mukherjee, N. ♦ Neerkundar, V. ♦ Patyra, M. ♦ Rajski, J. ♦ Tyszer, J. ♦ Zawada, J.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2015
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Circuit faults ♦ Logic gates ♦ Automatic test pattern generation ♦ Measurement ♦ Signal resolution ♦ Correlation ♦ FinFETs
Abstract The introduction of FinFET technology has accelerated the adoption of patterns that target cell internal defects such as cell-aware tests. Even though cell-aware tests can replace stuck-at and transition patterns from the screening point of view, we have to address the increase in test data volume. This combined with the growing gate counts enabled by new technology nodes is driving the need for even greater compression levels. In this paper, we present a novel test points technology designed to reduce deterministic pattern counts for cell-aware tests. The technology is based on identification and resolution of conflicts across internal signals allowing ATPG to significantly increase the number of faults targeted by a single pattern. Experimental results on a number of industrial designs with test compression demonstrate that the proposed test points are effective in achieving, on average, a 3×-4× multiplicative increase in compression for 1-cycle and 2-cycle cell-aware patterns.
Description Author affiliation: Intel Corp., Hillsboro, OR, USA (Acero, C.; Feltham, D.; Patyra, M.) || Poznan Univ. of Technol., Poznań, Poland (Tyszer, J.; Zawada, J.) || Mentor Graphics Corp., Wilsonville, OR, USA (Hapke, F.; Moghaddam, E.; Mukherjee, N.; Neerkundar, V.; Rajski, J.)
ISBN 9781467365789
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2015-10-06
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 1.09 MB
Page Count 8
Starting Page 1
Ending Page 8


Source: IEEE Xplore Digital Library