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Author Dai, Z.J. ♦ Asada, K.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1990
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Circuit topology ♦ Delay effects ♦ Capacitance ♦ Circuit synthesis ♦ Optimization methods ♦ Logic functions ♦ Very large scale integration ♦ Application specific integrated circuits ♦ Integrated circuit synthesis ♦ Strontium
Abstract A synthesis method for area-minimum multi-stage complex gates is proposed. It is based on a novel transistor-level multistage decomposition and transistor sizing method. A large single-stage complex gate is topologically decomposed into multistage circuits recursively. After the topology decompositions, transistor sizes of decomposed circuits are optimized using a two-step sizing method in order, to evaluate the real area-minimum circuit topology for given delay time and load capacitance. Experimental results are given to demonstrate that the proposed method can successfully generate the most area-efficient topology while simultaneously optimizing the sizes of transistors.<<ETX>>
Description Author affiliation: Dept. of Electr. Eng., Tokyo Univ., Japan (Dai, Z.J.; Asada, K.)
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1990-05-13
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 368.55 kB


Source: IEEE Xplore Digital Library