Thumbnail
Access Restriction
Subscribed

Author Simmons, S.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1999
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Random access memory ♦ Predictive models ♦ Semiconductor device modeling ♦ Integrated circuit yield ♦ Fabrication ♦ Integrated circuit modeling ♦ Virtual manufacturing ♦ Profitability ♦ History ♦ Testing
Abstract This paper presents a modeling technique for predicting DRAM die-per-wafer yield throughout a product's fabrication life cycle. Using manufacturing yield data, it is shown that an accurate mature yield prediction for a wide range of product types can be made by modifying the standard Poisson yield model to account for defect clustering, minimum dimension, and process complexity. It is also shown that an invariable learning factor can be derived using a learning curve equation based on average fabrication cycle time. This derivation leads to an accurate yield forecast through time.
Description Author affiliation: Micron Technol. Inc., Boise, ID, USA (Simmons, S.)
ISBN 0780354036
ISSN 1523553X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1999-10-11
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 225.26 kB
Page Count 4
Starting Page 123
Ending Page 126


Source: IEEE Xplore Digital Library