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Author Girard, P. ♦ Guiller, L. ♦ Landrault, C. ♦ Pravossoudovitch, S.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2000
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Test pattern generators ♦ Built-in self-test ♦ Circuit testing ♦ Energy consumption ♦ System testing ♦ Automatic testing ♦ Power generation ♦ Very large scale integration ♦ Power system reliability ♦ Packaging
Abstract A new BIST TPG design that is comprised of an Adjacency-based TPG plus a conventional pseudo-random TPG (i.e. a LFSR) is presented in this paper. When used to generate test patterns for test-per-clock BIST, it reduces the number of transitions that occur in the CUT and hence decreases the average and peak power consumption during testing. Moreover, the total energy consumption during BIST is also reduced since the test length produced by the mixed TPG is roughly the same as the test length produced by a classical LFSR-based TPG to reach the same fault coverage. Note that this TPG design has been developed to deal with strongly connected circuits with a small number of inputs.
Description Author affiliation: Lab. d'Inf. de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France (Girard, P.)
ISBN 0769508871
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2000-12-06
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 635.57 kB
Page Count 6
Starting Page 459
Ending Page 464

Source: IEEE Xplore Digital Library