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Author Yi-Siou Chen ♦ Lih-Yih Chiou ♦ Hsun-Hsiang Chang
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2011
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Resource management ♦ Computer architecture ♦ Estimation ♦ Analytical models ♦ Computational modeling ♦ Syntactics ♦ Wires
Abstract Performance estimation at system-level involves quantitative analysis to allow designers to evaluate alternative architectures before implementation. However, designers must spend a tremendous amount of time in system remodeling for performance estimation for each alternative solution in a huge design space. The effort required for system remodeling prolongs the exploration step. Furthermore, the accuracy and speed of performance analysis affects the effectiveness of architectural exploration. This work presents an architectural performance analysis using a dynamic trace-based method (APDT) to reduce the effort required for system remodeling and the time required to estimate performance during architecture exploration, thereby improving the effectiveness of that exploration. Experimental results demonstrate that the APDT approach is faster than the bus functional-level simulation on CoWare with a minor average deviation.
Description Author affiliation: Dept. of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan (Yi-Siou Chen; Lih-Yih Chiou; Hsun-Hsiang Chang)
ISBN 9781424475155
ISSN 21536961
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2011-01-25
Publisher Place Japan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
e-ISBN 9781424475162
Size (in Bytes) 260.35 kB
Page Count 6
Starting Page 591
Ending Page 596


Source: IEEE Xplore Digital Library